The invention relates to computer systems and, more particularly, to computer systems having multiple processors interconnected by a bus and having the capability to initiate an access command to a resource.
Modern computer system have multiple processors, memory resources, and input/output (I/0) devices interconnected by a common bus to achieve high total computational power. Such construction can provide very powerful systems capable of executing many millions of instructions per second. However, the interconnection of multiple processors can create difficulties when multiple processors simultaneously attempt to access memory or I/0 resources. For example, problems can develop when several processors each attempt a read-modify-write (RMW) operation. In an RMW operation, one processor retrieves data from a memory location, performs an operation on the data, and writes the modified data back to the original memory location. Unpredictable results affecting system integrity can occur if one processor has started an RMW operation for one memory location, and a second processor attempts an RMW operation for the same memory location in the time period between the "read" operation of the first processor's RMW operation and the "write" portion of that RMW operation.
One way to prevent multiple processors from performing RMW operations on the same memory locations is to provide an exclusive access command such as an "interlock read" command. This involves the use of a "lock" indicator, such as a lock bit, which is set when the "read" portion of an RMW operation is performed and which is reset after the "write" portion of the RMW operation is completed. A second processor attempting to initiate an RMW operation on a location in memory when the lock bit is set will cause the memory to return lock status information. The lock status information indicates to the processor that the second interlock read command was not accepted by the memory.
The interlock read operation alleviates problems caused by multiple processors each attempting to perform an RMW operation. Processors are granted equitable access to the bus for such interlock read operations by arbitration processes using, for example, a round-robin algorithm. However, performance bottlenecks can still occur. For example, under certain bus traffic conditions, a specific processor may repeatedly encounter locked memory locations and will be unable to obtain needed access to memory resources in a timely manner. Such problems are reduced by providing multiple lock bits for a memory module with each lock bit associated with a portion of the memory module rather than with the whole memory module. Such multiple lock bits provide finer "granularity" of interlocked read operations on a memory module, tying up a smaller portion of memory after an interlock read operation. A system including multiple lock bits is described in copending U.S. Pat. application, Ser. No. 07/044,954.
This solution also permits a higher success rate of RMW operations, thus improving system throughput. However, under certain conditions, selected processors can still encounter memory access problems. Bus arbitration can assist nodes to obtain adequate access to the system bus by providing such nodes with equitable access to the system bus. However, under certain conditions, such equitable bus access does not insure adequate access to the memory itself. For example, two or more processors performing interlock read commands at the same time can become synchronized with interlock read commands from other nodes in such a way that certain processors only present commands to the memory at times when memory has been locked by other nodes, such that those processors are effectively denied access to the memory resource.
A second example involving prolonged denial of system resources on a multiple processor system is when multiple processors attempt to access an I/0 bus at a higher rate than an I/0 adapter can serve such requests. The input queue of the I/0 adapter thus rapidly fills, resulting in "no acknowledge" (NACK) indications to processors attempting to subsequently access the I/0 bus.
Although the preceding discussion has emphasized the operation of a computer system employing processor nodes, memory nodes, and I/0 nodes, a more general discussion of such a system is in the terms of commander nodes, that is, nodes which initiate a transaction on a bus, and responder nodes, that is, nodes which respond to a transaction initiated by a commander node. At various times, a single device can function as either a commander node or a responder node.